This invention relates generally to a 6F2 DRAM array with apparatus for stress testing an isolation gate and method.
The reduction in memory cell and other circuit size required for high density dynamic random access memories (DRAMs) and other circuitry is a continuing goal in semiconductor fabrication. Implementing electric circuits involves connecting isolated devices through specific electric paths. When fabricating silicon and other material into integrated circuits, it is necessary to electrically isolate devices built into the substrate from one another. Electrical isolation of devices as circuit density increases is a continuing challenge.
One method of isolating devices involves the formation of a semi-recessed or fully recessed oxide in the non-active (or field) area of the substrate. These regions are typically termed as xe2x80x9cfield oxidexe2x80x9d and are formed by LOCal Oxidation of exposed Silicon, commonly known as LOCOS. One approach in forming such oxide is to cover the active regions with a layer of silicon nitride that prevents oxidation from occurring therebeneath. A thin intervening layer of a sacrificial pad oxide is provided intermediate the silicon substrate and nitride layer to alleviate stress and protect the substrate from damage during subsequent removal of the nitride layer. The unmasked or exposed field regions of the substrate are then subjected to a wet (H2O) oxidation, typically at atmospheric pressure and at temperatures of around 1000xc2x0 C., for two to four hours. This results in field oxide growth where there is no masking nitride.
However, LOCOS structures do not necessarily lend themselves to progressively smaller feature sizes and/or increased densities. This is discussed to some extent in U.S. Pat. No. 5,700,733, filed on Jun. 27, 1995, entitled xe2x80x9cSemiconductor Processing Methods Of Forming Field Oxide Regions On A Semiconductor Substratexe2x80x9d and issued to M. Manning, the disclosure of which is incorporated herein by reference for its teachings and which is assigned to the assignee of this patent document.
The above-noted patent presents a technique for using shallow trench isolation (STI) to realize a compact and robust DRAM cell having an area of 8F2. However, increasing demand for yet more compact and robust memory designs has continued to drive demand for even smaller cell areas.
Another alternative isolation technique uses an isolation gate structure formed between adjacent memory cells. The isolation gate structure is biased to greatly reduce the number of mobile charge carriers in the semiconducting material beneath the isolation gate structure. This architecture has the advantage of providing extremely compact memory cells having an effective area of about 6F2 (compared, for example, to an area of about 8F2 for the LOCOS structures described above), resulting in a compact memory device. However, conventional isolation gate structures provide leakage charge which flows, at least in part, into the storage nodes of the memory device. The leakage charge, in turn, is a limiting factor in storage times between refresh cycles. Further, some types of defects not easily identified in normal testing regimes can limit the lifetime of the isolation structure and thus of the memory array formed using the isolation structure.
Additionally, for many gate-isolated DRAM structures, it may be necessary to use double row redundancy for replacement of rows of memory cells that include defects. This arises because a row that has been replaced, and thus includes storage nodes that are not being periodically refreshed or otherwise actively biased, includes memory cells that float to various voltages. In turn, this can cause a memory cell in a row that is separated from the row that has been replaced by only one isolation gate to behave inappropriately. As a result, at least some DRAMs employing isolation gates between some rows of memory cells also use an arrangement whereby both the row of memory cells that includes one or more defects, and the neighboring row that is isolated from that row by the isolation gate, are replaced with a pair of redundant rows of memory cells. In turn, this causes the DRAM integrated circuit to be larger than might be the case if other replacement arrangements for rows of memory cells that are defective were practicable.
Needed are apparatus and methods for improving robustness of isolation structures for improved, compact memory cells and memory cell arrays.
In a first aspect, the present invention includes a 6F2 DRAM array. The DRAM array includes a first memory cell, a second memory cell and an isolation gate formed between the first and second memory cells. The isolation gate is configured to provide electrical isolation between the first and second memory cells. The DRAM also includes a first switch having first and second load electrodes and a control electrode configured to accept a first control signal. The first load electrode is coupled to the isolation gate and the second load electrode is coupled to ground. The DRAM additionally includes a second switch having first and second load electrodes and a control electrode configured to accept a second control signal. The first load electrode is coupled to the isolation gate and the second load electrode is coupled to a stress voltage source.
In another aspect, the present invention includes a DRAM array. The DRAM array includes a first memory cell, a second memory cell and an isolation gate formed between the first and second memory cells. The isolation gate is configured to provide electrical isolation between the first and second memory cells. The DRAM array also includes a first transistor having first and second load electrodes and a control electrode. The control electrode is configured to accept a control signal. The first load electrode is coupled to the isolation gate and the second load electrode is configured to be coupled to a positive voltage.
In yet another aspect, the present invention includes a method of forming memory cells in a 6F2 DRAM array. The method includes forming a first memory cell, forming a second memory cell adjacent the first memory cell and forming an isolation gate between the first and second memory cells. The isolation gate is configured to provide electrical isolation between the first and second memory cells. The method also includes forming a first switch having first and second load electrodes and a control electrode. The control electrode is configured to accept a control signal. The first load electrode is coupled to the isolation gate and the second load electrode is configured to be coupled to a positive voltage.
In a further aspect, the present invention includes a method of stress testing an isolation gate formed between two rows of memory cells in a DRAM array. The method includes ensuring that a first switch coupled between the isolation gate and a first potential is OFF, toggling a second switch coupled between the isolation gate and a test potential ON and waiting for a predetermined interval. The method also includes toggling the second switch OFF, toggling the first switch ON and performing function testing of the DRAM array.
In a yet further aspect, the present invention includes a method of isolating a single row of memory cells in a 6F2 DRAM array. The method includes providing pairs of rows of memory cells and providing an isolation gate separating rows comprising each pair of rows. Each isolation gate is configured to isolate one of the pair of rows from another of the pair of rows. The method also includes providing a transistor having a load electrode coupled to the isolation gate. The transistor is configured to supply a suitable voltage to the isolation gate to isolate one of the pair of rows from another of the pair of rows in response to a control signal.
In another aspect, the present invention includes a computer system. The computer system includes a central processing unit, an input interface and a memory device coupled to the central processing unit. The memory device is configured to store instructions and data for use by the central processing unit. The memory device includes a DRAM array including a first memory cell, a second memory cell and an isolation gate formed between the first and second memory cells. The isolation gate is configured to provide electrical isolation between the first and second memory cells. The DRAM array also includes a first transistor having first and second load electrodes and a control electrode. The control electrode is configured to accept a control signal. The first load electrode is coupled to the isolation gate and the second load electrode is configured to be coupled to a positive voltage.